Pulse width modulation (PWM) is the modulation of the duty cycle of a rectangular pulse signal. Pulse width modulation circuitry may be adapted to generate a rectangular pulse output signal with a duty cycle that is controlled by an analog input voltage. This PWM circuitry has numerous applications in modern electronic devices, including power regulation and RF communications. Multiple configurations for PWM circuitry currently exist, including both analog and analog-to-digital designs.
One example of conventional PWM circuitry is shown in FIG. 1. FIG. 1 shows conventional analog PWM circuitry 10 including a comparator 12 and a ramp generator 14. The ramp generator 14 is adapted to generate a ramp signal V_RAMP. The comparator 12 is adapted to receive the ramp signal V_RAMP and an analog input voltage V_INPUT from an external source (not shown). The comparator 12 is further adapted to compare the ramp signal V_RAMP and the analog input voltage V_INPUT to produce a rectangular pulse output signal V_PWM. As is shown in the timing diagram, the rectangular pulse output signal V_PWM is at a logic-level high when then analog input voltage V_INPUT is greater than the ramp signal V_RAMP, and at a logic-level low when the analog input voltage V_INPUT is less than the ramp signal V_RAMP. Accordingly, the conventional analog PWM circuitry 10 generates the rectangular pulse output signal V_PWM with a modulated duty cycle that is controlled by the analog input voltage V_INPUT.
Although suitable for some PWM applications, the conventional analog pulse width modulation circuitry 10 suffers from low efficiency, high noise, and marginal reliability. The ramp generator 14 consumes a large amount of power, especially at high frequencies. Further, the ramp generator 14 is susceptible to noise of surrounding circuitry.
An additional example of conventional PWM circuitry is shown in FIG. 2. FIG. 2 shows conventional analog-to-digital PWM circuitry 16, including a binary analog-to-digital converter 18, clock generator circuitry 20, and a counter 22. The binary analog-to-digital converter 18 is adapted to receive an analog input voltage V_INPUT and produce a binary coded digital value B_CODE that is representative of the amplitude of the analog input voltage V_INPUT. The clock generator circuitry 20 is adapted to generate a clock signal CLK and a strobe control signal STROBE for driving the counter 22. When the strobe control signal STROBE experiences a rising edge, the counter 22 generates a voltage at the output of the conventional analog-to-digital PWM circuitry 16, corresponding with a logic-level high signal, as is shown in the timing diagram. The counter 22 then counts each clock cycle of the clock signal CLK and continues to generate a voltage at the output until a number of clock cycles determined by the binary coded digital value B_CODE have passed. Once the correct number of clock cycles have passed, the counter 22 ceases to generate a voltage at the output of the conventional analog-to-digital PWM circuitry 16, corresponding with a logic-level low signal, as is shown in the timing diagram. Accordingly, the conventional analog-to-digital PWM circuitry 16 generates a rectangular pulse output signal V_PWM with a modulated duty cycle that is controlled by the analog input voltage V_INPUT.
Although suitable for some PWM applications, the conventional analog-to-digital PWM circuitry 16 may be expensive or impractical to operate at high frequencies. At high operating frequencies, the counter 22 must operate at a very high speed in order to effectively count each clock cycle. A high speed counter may increase the cost of the conventional analog-to-digital PWM circuitry 16, and may consume large amounts of power. Further, due to the binary encoding of the analog input voltage V_INPUT, the conventional analog-to-digital PWM circuitry 16 is highly sensitive to errors. Because of the weighted nature of binary encoding, an error in a single bit of the binary coded digital value B_CODE has the potential to produce up to a 50% margin of error in the pulse width of the rectangular pulse output signal V_PWM. This is known as a “most significant bit” error, and is problematic for many applications that demand precise control over the rectangular pulse output signal V_PWM.
An additional example of conventional PWM circuitry is shown in FIG. 3. FIG. 3 shows conventional analog-to-digital PWM circuitry 24 including a binary analog-to-digital converter 26, a binary decoder 28, clock generator circuitry 30, and an output stage 32. The binary analog-to-digital converter 26 is adapted to receive an analog input voltage V_INPUT and produce a binary coded digital value B_CODE that is representative of the amplitude of the analog input voltage V_INPUT. The clock generator circuitry 30 is adapted to generate a reference clock signal REF_CLK and a plurality of delayed clock signals DEL_CLKS for presentation to the binary decoder 28. The binary decoder 28 is adapted to receive and decode the binary coded digital value B_CODE, and select a delayed clock signal SDEL_CLK from the plurality of delayed clock signals DEL_CLKS based upon the decoded binary digital value B_CODE. The selected delayed clock signal SDEL_CLK is delivered to the output stage 32, where it is used in combination with the reference clock signal REF_CLK to generate a rectangular pulse output signal V_PWM with a modulated duty cycle that is controlled by the analog input voltage V_INPUT.
Although suitable for some PWM applications, the conventional analog-to-digital PWM circuitry 24 suffers from latency errors introduced as a result of the binary encoding and decoding of the analog input voltage V_INPUT.
Because both the binary analog-to-digital converter 26 and the binary decoder 28 take at least one clock cycle to generate their respective output signals, the rectangular pulse output signal V_PWM will be delayed by at least one clock cycle with respect to changes in the analog input voltage V_INPUT. This error is often referred to as a “Z-1 error,” and is difficult to correct. In applications where timing is crucial to the operation of the device, the described error may render the device inoperable or unstable. Further, due to the binary encoding and decoding of the analog input voltage V_INPUT, the conventional analog-to-digital PWM circuitry 24 suffers from the same error sensitivity as described above with respect to FIG. 2. Accordingly, there is a need for PWM circuitry that is efficient and noise-immune while avoiding latency errors.